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PD - 94404
SMPS MOSFET
IRLR8203 IRLU8203
HEXFET(R) Power MOSFET
Applications l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use l High Frequency Buck Converters for Computer Processor Power Benefits
l l l
VDSS
30V
RDS(on) max
6.8m
ID
110A
Ultra-Low Gate Impedance Very Low RDS(on) at 4.5V VGS Fully Characterized Avalanche Voltage and Current
D-Pak IRLR8203
I-Pak IRLU8203
Absolute Maximum Ratings
Symbol
VDS VGS ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C PD @TC = 100C TJ , TSTG
Parameter
Drain-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Junction and Storage Temperature Range
Max.
30 20 110 76 120 140 69 0.92 -55 to + 175
Units
V V A W W W/C C
Thermal Resistance
Parameter
RJC RJA RJA Junction-to-Case Junction-to-Ambient (PCB mount)* Junction-to-Ambient
Typ.
--- --- ---
Max.
1.09 50 110
Units
C/W
* When mounted on 1" square PCB (FR-4 or G-10 Material) . For recommended footprint and soldering techniques refer to application note #AN-994
Notes through are on page 10
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IRLR/U8203
Static @ TJ = 25C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient V(BR)DSS RDS(on) VGS(th) IDSS IGSS Min. Typ. Max. Units Conditions 30 --- --- V VGS = 0V, ID = 250A --- 0.027 --- V/C Reference to 25C, ID = 1mA --- 5.6 6.8 VGS = 10V, ID = 15A m Static Drain-to-Source On-Resistance --- 7.1 9.0 VGS = 4.5V, ID = 12A Gate Threshold Voltage 1.0 --- 3.0 V VDS = V GS, ID = 250A --- --- 20 VDS = 24V, VGS = 0V A Drain-to-Source Leakage Current --- --- 100 VDS = 24V, VGS = 0V, TJ = 125C Gate-to-Source Forward Leakage --- --- 200 VGS = 20V nA Gate-to-Source Reverse Leakage --- --- -200 VGS = -20V
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qoss td(on) tr td(off) tf Ciss Coss Crss Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Output Gate Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. 35 --- --- --- --- --- --- --- --- --- --- --- Typ. --- 33 5.7 17 23 15 99 30 69 2430 1200 250 Max. Units Conditions --- S VDS = 15V, ID = 12A 50 ID = 12A 8.5 nC VDS = 24V 25 VGS = 4.5V 34 VGS = 0V, VDS = 10V --- VDD = 15V --- ID = 12A ns --- RG = 6.8 --- VGS = 4.5V --- VGS = 0V --- VDS = 15V --- pF = 1.0MHz
Avalanche Characteristics
Symbol
EAS IAR
Parameter
Single Pulse Avalanche Energy Avalanche Current
Typ.
--- ---
Max.
310 30
Units
mJ A
Diode Characteristics
Symbol
IS
ISM
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Reverse Reverse Reverse Recovery Recovery Recovery Recovery Time Charge Time Charge
Min. Typ. Max. Units --- --- --- --- --- --- --- --- --- 110 A --- 0.75 0.65 48 62 49 67 120 1.3 --- 72 92 74 100 V ns nC ns nC
VSD trr Qrr trr Qrr
Conditions D MOSFET symbol showing the G integral reverse S p-n junction diode. TJ = 25C, IS = 12A, VGS = 0V TJ = 125C, IS = 12A, VGS = 0V TJ = 25C, I F = 12A, VR=15V di/dt = 100A/s TJ = 125C, IF = 12A, VR=15V di/dt = 100A/s
2
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IRLR/U8203
1000
VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V TOP
1000
ID , Drain-to-Source Current (A)
100
ID , Drain-to-Source Current (A)
100
VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V TOP
2.5V
10
10
2.5V
20s PULSE WIDTH Tj = 25C
1 0.1 1 10 100 1 0.1 1
20s PULSE WIDTH Tj = 175C
10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.00
2.0
I D = 30A
ID , Drain-to-Source Current ( )
1.5
RDS(on) , Drain-to-Source On Resistance
100.00
T J = 25C T J = 175C
(Normalized)
1.0
0.5
10.00 2.0 3.0
VDS = 15V 20s PULSE WIDTH
4.0 5.0
0.0 -60 -40 -20 0 20 40 60 80
V GS = 10V
100 120 140 160 180
TJ , Junction Temperature
( C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRLR/U8203
10000 VGS = 0V, f = 1 MHZ Ciss = C + C , C gs gd ds SHORTED Crss = C gd Coss = C + C ds gd
6
I D = 12A
5
V DS = 24V V DS = 15V V DS = 6V
C, Capacitance(pF)
Ciss Coss
1000
VGS, Gate-to-Source Voltage (V)
4
3
2
Crss
1
100 1 10 100
0 0 10 20 30 40
VDS , Drain-to-Source Voltage (V)
Q G, Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
1000 OPERATION IN THIS AREA LIMITED BY R DS (on)
100
TJ = 175 C
10
ID, Drain-to-Source Current (A)
I SD, Reverse Drain Current (A)
100 100sec
1
TJ = 25 C
10 Tc = 25C Tj = 175C Single Pulse 1 0 1 10
1msec 10msec
0.1 0.2 0.4 0.6 0.8 1.0
V GS = 0 V
1.2 1.4
100
1000
V SD,Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRLR/U8203
120
LIMITED BY PACKAGE
100
VDS VGS RG
RD
D.U.T.
+
80
-VDD
ID , Drain Current (A)
4.5V
60
Pulse Width 1 s Duty Factor 0.1 %
40
Fig 10a. Switching Time Test Circuit
VDS 90%
20
0 25 50 75 100 125 150 175
TC , Case Temperature
( C)
10% VGS
Fig 9. Maximum Drain Current Vs. Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
10
(Z thJC )
1 D = 0.50
Thermal Response
0.20 0.10 0.1 0.05 0.02 0.01
SINGLE PULSE (THERMAL RESPONSE) 0.0001 0.001 0.01
0.01 0.00001
Notes: 1. Duty factor D = 2. Peak T
J
P DM t1 t2 +TC 1
t1 / t 2
= P DM x Z thJC 0.1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRLR/U8203
1 5V 800
VDS
L
D R IV E R
600
ID TOP 12A 21A 30A BOTTOM
RG
20V tp
D .U .T
IA S
+ V - DD
A
E AS , Single Pulse Avalanche Energy (mJ)
400
0 .0 1
Fig 12a. Unclamped Inductive Test Circuit
200
V (B R )D SS tp
0 25 50 75 100 125 150 175
Starting Tj, Junction Temperature
( C)
IAS
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
QG
50K 12V .2F .3F
4.5 V
QGS VG QGD
D.U.T. VGS
3mA
+ V - DS
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRLR/U8203
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET(R) Power MOSFETs
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IRLR/U8203
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
6 .7 3 (.2 6 5 ) 6 .3 5 (.2 5 0 ) -A5 .4 6 (.2 1 5 ) 5 .2 1 (.2 0 5 ) 4 1 .2 7 (.0 5 0 ) 0 .8 8 (.0 3 5 )
2 .3 8 (.0 9 4 ) 2 .1 9 (.0 8 6 )
1 .1 4 (.0 4 5 ) 0 .8 9 (.0 3 5 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 )
6 .4 5 (.2 4 5 ) 5 .6 8 (.2 2 4 ) 6 .2 2 (.2 4 5 ) 5 .9 7 (.2 3 5 ) 1.0 2 (.0 4 0 ) 1.6 4 (.0 2 5 ) 1 2 3 0 .5 1 (.0 2 0 ) M IN . 1 0 .4 2 (.4 1 0 ) 9 .4 0 (.3 7 0 )
L E A D A S S IG N M E N T S 1 - GATE 2 - D R A IN 3 - S OU R CE 4 - D R A IN
-B 1 .5 2 (.0 6 0 ) 1 .1 5 (.0 4 5 ) 1 .1 4 (.0 4 5 ) 0 .7 6 (.0 3 0 ) 2 .2 8 ( .0 9 0 ) 4 .5 7 ( .1 8 0 ) 0 .8 9 (.0 3 5 ) 3X 0 .6 4 (.0 2 5 ) 0 .2 5 ( .0 1 0 ) M AMB N O TE S :
2X
0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 )
1 D IM E N S IO N IN G & T O L E R A N C IN G P E R A N S I Y 1 4 .5 M , 1 9 8 2 . 2 C O N T R O L L IN G D IM E N S IO N : IN C H . 3 C O N F O R M S T O J E D E C O U T L IN E T O -2 5 2 A A . 4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP , S O L D E R D IP M A X. + 0 .1 6 (.0 0 6 ) .
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120 WIT H ASSEMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN T HE ASSEMBLY LINE "A" PART NUMBER INT ERNAT IONAL RECT IFIER LOGO
IRFU120 916A 12 34
ASSEMBLY LOT CODE
DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A
8
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IRLR/U8203
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6 .7 3 (.26 5 ) 6 .3 5 (.25 0 ) -A 5 .4 6 (.2 1 5 ) 5 .2 1 (.2 0 5 ) 4 1 .2 7 ( .0 5 0 ) 0 .8 8 ( .0 3 5 )
2 .3 8 (.0 9 4 ) 2 .1 9 (.0 8 6 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 ) L E A D A S S IG N M E N T S 1 - GATE 2 - D R A IN 3 - SOURCE 4 - D R A IN
6 .4 5 (.2 4 5 ) 5 .6 8 (.2 2 4 ) 1 .5 2 (.0 6 0 ) 1 .1 5 (.0 4 5 ) 1 -B 2.2 8 (.0 9 0) 1.9 1 (.0 7 5) 9 .6 5 ( .3 8 0 ) 8 .8 9 ( .3 5 0 ) 2 3 6 .2 2 ( .2 4 5 ) 5 .9 7 ( .2 3 5 )
N O TE S : 1 D IM E N S IO N IN G & TO L E R A N C IN G P E R A N S I Y 1 4 .5M , 19 8 2 . 2 C O N T R O L L IN G D IM E N S IO N : IN C H . 3 C O N F O R MS TO J E D E C O U T L IN E TO -2 5 2 A A . 4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP , S O L D E R D IP M A X. + 0.1 6 (.0 0 6 ).
3X
1 .1 4 (.0 45 ) 0 .7 6 (.0 30 )
3X
0 .8 9 (.0 35 ) 0 .6 4 (.0 25 ) M AMB
1 .1 4 ( .0 4 5 ) 0 .8 9 ( .0 3 5 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 )
2 .28 (.0 9 0 ) 2X
0 .2 5 (.0 1 0 )
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120 WIT H ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 19, 1999 IN T HE ASSEMBLY LINE "A" PART NUMBER INT ERNAT IONAL RECT IFIER LOGO
IRFU120 919A 56 78
DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A
ASSEMBLY LOT CODE
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IRLR/U8203
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TR L
1 6 .3 ( .6 4 1 ) 1 5 .7 ( .6 1 9 )
1 6 .3 ( .64 1 ) 1 5 .7 ( .61 9 )
1 2 .1 ( .4 7 6 ) 1 1 .9 ( .4 6 9 )
FE E D D IR E C TIO N
8 .1 ( .3 18 ) 7 .9 ( .3 12 )
FE E D D IR E C T IO N
N O T ES : 1 . C O N T R O L L IN G D IM EN S IO N : M IL L IM ET E R . 2 . AL L D IM EN SIO N S AR E SH O W N IN M IL L IM ET E R S ( IN C H E S ). 3 . O U TL IN E C O N F O R M S T O E IA -4 81 & E IA -54 1 .
1 3 IN C H
16 m m N O T ES : 1 . O U TL IN E C O N F O R M S T O E IA-4 8 1 .
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Pulse width 400s; duty cycle 2%. Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
Starting TJ = 25C, L = 0.68mH
RG = 25, IAS = 30A.
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.03/02
10
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